1. Technical Field
The present invention relates to a semiconductor memory device, and more particularly, to the semiconductor memory device which includes a sense amplifier to write data at high speed.
2. Description of the Related Art
FIG. 1 is a circuit diagram of a conventional sense amplifier.
The sense amplifier 100 shown in FIG. 1 includes a bit line 101 and complementary bit line 102 pair and a data input/output line 103 and complementary data input/output line 104 pair to write data in memory cells and read the data stored in the memory cells.
The data input/output line 103 is connected to the bit line 101 via a first N-channel metal oxide semiconductor (NMOS) transistor 105 and the complementary data input/output line 104 is connected to the complementary bit line 102 via a second NMOS transistor 106. And a write column select line enable signal WCSL is input to the gate of the first NMOS transistor 105 and the gate of the second NMOS transistor 106.
Also, an equalizer 107 is connected between the bit line 101 and the complementary bit line 102. The equalizer 107 includes NMOS transistors 108 through 110. An enabled equalizer signal EQ is input to the equalizer 107 through the gates of the NMOS transistors 108 through 110 and the voltages of both the bit line 101 and the complementary bit line 102 are pre-charged to one half of a power supply voltage VCC by inputting a voltage signal VBL of the voltage VCC/2.
An amplifier 111, the bit line 101, and the complementary bit line 102 are connected through a select gate 112. The select gate 112 includes NMOS transistors 113 and 114 and the NMOS transistors 113 and 114 receive a left isolation signal ISOL via the gates of the NMOS transistors 113 and 114.
The amplifier 111 includes a plurality of transistors 105, 106, and 115 through 118 connected to the data input/output line 103 and the complementary data input/output line 104. Also, the amplifier 111 includes two NMOS transistors 119 and 120 and two P-channel metal oxide semiconductor (PMOS) transistors 121 and 122 to amplify data. The two transistors 115 and 116 are connected in series between a ground voltage VSS and the data input/output line 103 and the two transistors 117 and 118 are connected in series between the ground voltage VSS and the complementary data input/output line 104. Also, a read column select line enable signal RCSL is connected to the gates of the two transistors 116 and 118.
The gate of the NMOS transistor 119 connected to the bit line 101 is connected to the complementary bit line 102, and the gate of the NMOS transistor 120 connected to the complementary bit line 102 is connected to the bit line 101. A complementary sense amplifier enable signal SAB is input to the common contact of the two NMOS transistors 119 and 120.
The gate of the PMOS transistor 121 connected to the bit line 101 is connected to the complementary bit line 102, and the gate of the PMOS transistor 122 connected to the complementary bit line 102 is connected to the bit line 101. A sense amplifier enable signal SA is input to the common contact of the two PMOS transistors 121 and 122.
Also, another equalizer 124 and select gate 123 corresponding to the equalizer 107 and select gate 112 exist at the other end. The bit line 101 and complementary bit line 102 are connected to a plurality of memory cells (not shown), respectively. Thereby, data in the plurality of memory cells can be read and/or written using one sense amplifier.
FIG. 2 is a timing diagram for a write operation of the sense amplifier 100 shown in FIG. 1.
With reference to FIGS. 1 and 2, when the equalizer signal EQ is enabled to a high level, the transistors 108 through 110 are turned on, the voltage of the bit line 101 becomes the same as that of the complementary bit line 102, and both of the bit line 101 and the complementary bit line 102 are pre-charged to the voltage VCC/2 by inputting the VCC/2 voltage signal VBL.
Next, when the left isolation signal ISOL is enabled to the high level, the NMOS transistors 113 and 114 are turned on. Then, data can be written in and/or read from the memory cell on the left side of the sense amplifier 100. And when a right isolation signal ISOR stays at the low level, the bit line pair connected to the memory cells on the right side of the sense amplifier 100 remains in a non-selected state.
Next, when the equalizer signal EQ changes to the low level, the bit line pair 101 and 102 are in a floating state. And when a word line signal (not shown) is enabled, the voltage of the bit line 101 is changed by the data in the memory cell connected to the word line and the bit line 101. Meanwhile, the sense amplifier enable signal SA becomes the high level and the complementary sense amplifier enable signal SAB becomes the low level.
For example, if the memory cell connected to the bit line 101 has data of the low level, the voltage of the bit line 101 is a little lower than the voltage VCC/2. In that case, since the voltage of the complementary bit line 102 is higher than that of the bit line 101, the NMOS transistor 119 is turned-on, the NMOS transistor 120 is turned-off, the PMOS transistor 121 is turned-off, and the PMOS transistor 122 is turned-on. Therefore, since the voltage of the complementary bit line 102 goes to the high level (for example, the power supply voltage VCC) and the voltage of the bit line 101 goes to the ground voltage VSS, a data signal is amplified.
Then, when the write column select line enable signal WCSL is enabled to the high level, the data input/output line pair 103 and 104 and the bit line pair 101 and 102 are connected to each other. If the data input/output line 103 is at the high level and the complementary data input/output line 104 is at the low level, the on/off states of the NMOS transistors 119 and 120 and the PMOS transistors 121 and 122 in the sense amplifier 100 are changed into the opposite states, respectively. Therefore, the data level of the bit line 101 becomes equal to that of the data input/output line 103 and the data level of the complementary bit line 102 becomes equal to that of the complementary data input/output line 104. Accordingly, the data of the data input/output line 103 is written in the memory cell via the bit line 101.
The equalizer signal EQ becomes the high level after the data is written, and the bit line pair 101 and 102 is pre-charged.
Recently, according to a high speed dynamic random access memory (DRAM) operation, reduction in a data read/write cycle time is required for a semiconductor memory device.
However, in the conventional semiconductor memory, if the write column select line enable signal WCSL is at the high level without first amplifying data when the data is input to a selected bit line pair in a data write cycle, data of an adjacent bit line pair may be changed. That is, since, before the data is amplified the voltage of the data of a selected bit line are similar to each other, the voltage of the data may be changed by a high level voltage of an adjacent bit line.
Therefore, until the data value is restored to a voltage level sufficient to prevent the voltage level of an adjacent bit line pair from influencing a voltage level of the data value of the selected bit line, the data value of the selected bit line must be amplified by the amplifier. That is, while the amplifier amplifies the data so that the data value becomes around 500 mV, the write column select line enable signal WCSL must stay at the low level. Therefore, since the data cannot be written while the amplifier is amplifying the data, the write operation is delayed comparing to the read cycle time. Accordingly, the delay time is an obstacle to a high speed semiconductor memory device.
Also, in a data input/output (IO) structure for a high speed device in a conventional DRAM, 8 column select lines (CSLs) are connected to one data IO line pair. Also, an IO multiplexing function makes a wide IO scheme possible. If the wide IO mode is supported from the ×256 mode to the ×16 mode, data IO lines selected in only the ×128/×64/×32/×16 modes, not the ×256 mode, are active. However, at this time, since transistors connected to all CSLs are also open, current flow is induced in non-selected data IO lines. Accordingly, unnecessary power loss occurs.
Accordingly, it would be desirable to provide a semiconductor memory device including a sense amplifier circuit to write data at high speed in a memory cell of the semiconductor memory device.
It would also be desirable to provide a semiconductor memory device preventing power loss by preventing current flow of non-selected data input/output lines of data input/output lines using column select lines.
According to one aspect of the present invention a sense amplifier of a semiconductor memory device comprises a bit line and a complementary bit line; a data input/output line and a complementary data input/output line; first and second transistors which are connected in series between the data input/output line and the bit line; and third and fourth transistors which are connected in series between the complementary data input/output line and the complementary bit line, wherein a gate of the first transistor is connected to the complementary data input/output line, a gate of the third transistor is connected to the data input/output line, and a write column select line enable signal is input to the gates of the second and fourth transistors.
According to another aspect of the present invention, a sense amplifier of a semiconductor memory device comprises a bit line and a complementary bit line; a data input/output line and a complementary data input/output line; first and second transistors which are connected in series between the data input/output line and the bit line, each of the first and second transistors having a first terminal, a second terminal, and a gate; and third and fourth transistors which are connected in series between the complementary data input/output line and the complementary bit line, each of the third and fourth transistors having a first terminal, a second terminal, and a gate, wherein a write column select line enable signal is input to the gates of the first and third transistors, wherein one of the first and second terminals of the first transistor is connected to the gate and to one of the first and second terminals of the second transistor, and wherein one of the first and second terminals of the third transistor is connected to the gate and to one of the first and second terminals of the fourth transistor.
According to still another aspect of the present invention, a sense amplifier of a semiconductor memory device comprises a bit line and a complementary bit line; a data input/output line and a complementary data input/output line; first and second transistors which are connected in series between the data input/output line and the bit line; and third and fourth transistors which are connected in series between the complementary data input/output line and the complementary bit line, wherein a gate of the first transistor is connected to the data input/output line, a gate of the third transistor is connected to the complementary data input/output line, and a write column select line enable signal is input to gates of the second and fourth transistors.